2 Years Impact Factor:
2.85
5 Years Impact Factor: 1.53
Author: Adabala Lahari , Josh Joseph Empra , Ranga Sai Teja , Ms. Heena Kauser
Abstract:
Finite Impulse Response (FIR) filters are essential components in digital signal processing (DSP) applications due to their stability and linear phase characteristics. However, traditional FIR filter designs often face challenges such as high-power consumption, increased area utilization, and significant delays, particularly in high-performance applications. This paper proposes an optimized FIR filter architecture utilizing inner product units and parallel accumulation techniques to address these challenges. The proposed design incorporates pipelined adders, coefficient storage units, and parallel processing to achieve significant improvements in power efficiency, area optimization, and computational speed. Experimental results obtained using Xilinx Vivado demonstrate a 30% reduction in LUT usage, a 20% decrease in power consumption, and a 27.2% improvement in delay metrics compared to existing systems. The enhanced architecture is ideal for real-time DSP applications in fields
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